feat(scheduler-core): implement what-if branching and simulation output recording (task 11.5)
Add sim_record.c (scheduler_t-free .replay writer: ReplayHeader + loaded SnapshotEntry once, then per-event pass-through and per-session ReplaySession finalization) and wire --sim-alt-events event-source selection into sim_loop.c's drain loop, coexisting with task 11.2's stdout default and task 11.4's --sim-verify. Extract scheduler_t-free halves out of recording_session.c's begin/end so sim-side code can reuse the decision-encoding path without gaining an xce_scheduler_t* dependency, preserving Req 5 AC 17 isolation. Per Req 5 AC 16/19.
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14 changed files with 1750 additions and 91 deletions
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@ -52,6 +52,19 @@
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* it; this task only stores it)
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* bool interactive; -- --interactive/-i (task 12 acts on
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* it; this task only stores it)
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*
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* `snapshot_ts` below is ONE field beyond design.md's literal 8-field
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* struct sketch (scheduler-core spec, task 11.5, Req 5 AC 19) -- added, not
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* merely implied, because writing a `--sim-output` file's initial
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* SnapshotEntry needs the EXACT timestamp Step 2's snapshot scan
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* (sim_locate_and_load_snapshot(), sim.c) chose, and re-deriving it via
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* xce_core_now(&sim->core) from inside sim_loop.c's event loop is NOT
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* equivalent for any --sim-speed other than frozen (0): the virtual clock
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* keeps advancing with real wall-clock time between
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* sched_sim_driver_start() returning and sim_loop.c's first opportunity to
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* write the output header/snapshot, so a re-derived value would drift from
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* "the same SnapshotEntry that was loaded" (AC 19's own wording -- same ts,
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* not merely a same-shaped one taken moments later).
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*/
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typedef struct {
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xce_sched_core_t core;
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@ -62,6 +75,7 @@ typedef struct {
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uint64_t sim_speed_den;
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bool verify;
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bool interactive;
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uint64_t snapshot_ts;
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} xce_sched_sim_driver_t;
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/*
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